
module tb_toggle_sync();

 reg clk;
 reg reset_n;
 reg data_in;
 
 wire toggle_out;

 reg ff_d1, ff_d2;
 
 wire pulse_out;
 
 
 pulse_to_toggle uut(
  .clk (clk),
  .reset_n (reset_n),
  .data_in (data_in),

  .toggle_out (toggle_out)
  );

always @(posedge clk or negedge reset_n) begin
  
  if (!reset_n) begin
    ff_d1 <= 0;
    ff_d2 <= 0;
  end else begin
    ff_d1 <= toggle_out;
    ff_d2 <= ff_d1;
  end   
end


edge_detector uut2 (
  .clk (clk),
  .reset_n (reset_n),
  .data_in (ff_d2),
  .pulse_out (pulse_out)
);


initial begin
  
      clk = 0; 
      reset_n = 0;
      data_in = 0;
      #100
      reset_n = 1;
      
      #100
      
      data_in = 1;
      
      #10
      
      data_in = 0;
      
 end 
     
 always begin 
      #5  clk =   ~clk;
 end 
  

  
endmodule
